1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless copper deposition to fill the trench with copper.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that, to a great extent, substantially determines the performance capability of integrated circuit devices employing such transistors. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the semiconductor device and the overall functionality of the circuit.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, decreasing the size of, for instance, the channel length of a transistor typically results in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using aluminum for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
Copper is a material that is difficult to etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. In general, the damascene technique involves (1) forming a trench/via in a layer of insulating material, (2) depositing one or more relatively thin barrier layers, (3) forming copper material across the substrate and in the trench/via and (4) performing a chemical mechanical polishing process to remove the excess portions of the copper material and the barrier layer positioned outside of the trench/via to define the final conductive copper structure. The copper material is typically formed by performing an electrochemical copper deposition process after a thin conductive copper seed layer is deposited by physical vapor deposition on the barrier layer.
FIGS. 1A-1C depict one illustrative example of a problem that may be encountered when conductive copper structures are formed by performing an electroplating process to deposit bulk copper material. As shown in FIG. 1A, a hard mask or polish-stop layer 12 has been formed above a layer of insulating material 10, e.g., silicon dioxide, and a trench/via 14 has been formed in the layer of insulating material 10 by performing known photolithography and etching techniques. A barrier metal layer 16, e.g., tantalum nitride, tantalum or ruthenium, etc., has been deposited across the substrate and in the trench/via 14. Thereafter, a so-called copper seed layer 18 is blanket-deposited across the substrate and in the trench/via 14.
An electroplating process is then performed to deposit an appropriate amount of bulk copper, e.g., a layer of copper about 500 nm or so thick, across the substrate in an attempt to insure that the trench/via 14 is completely filled with copper. In an electroplating process, electrodes (not shown) are coupled to the copper seed layer 18 at the perimeter of the substrate and a current is passed through the copper seed layer 18 which caused copper material to deposit and build on the copper seed layer 18.
FIG. 1B depicts a problem that may be encountered in forming conductive copper structures using an electroplating process. As noted above, as device dimensions have continued to shrink, the size of the conductive structures has also decreased. As a result, the dimensions of the trench/via 14 have become relatively small, making it a challenge to reliably fill such high-aspect ratio openings with very small openings at the top. FIG. 1B depicts the copper seed layer 18 at a relatively early stage of the electroplating process. As the electroplating process proceeds, the copper material may tend to “pinch-off” the trench opening in the areas 19, thereby leading to the formation of an illustrative void 20. At least one reason why this occurs is because the deposition of copper in an electroplating process typically occurs in many directions, i.e., from all copper seed surfaces, although the rate at which copper deposits may be greater on some surfaces, e.g., more copper may deposit on the bottom of a trench as compared to the amount of copper deposited on the sidewalls of the trench. Thus, formation of copper material on the copper seed layer 18 positioned on the sidewalls of the trench/via 14 tends to contribute, to at least some degree, to the “pinch-off” problem.
FIG. 1C depicts the device 100 after at least one chemical mechanical polishing (CMP) process has been performed to remove excess material positioned outside of the trench/via 14 to thereby define the final conductive copper structure 22 having an illustrative void 20 formed therein. At a minimum, the presence of such voids 20 may increase the resistance of the conductive copper structure 22, may result in increased localized heating, and may reduce the overall operating efficiency of the integrated circuit product. In a worst-case scenario, the conductive copper structure 22 may even completely fail. In addition, the presence of such voids may make the copper structure 22 more susceptible to undesirable electromigration.
There are other problems associated with using an electroplating process to form layers of bulk copper when forming conductive copper structures. For example, as noted above, in an electroplating process, there is typically a relatively large quantity of copper material, e.g., at least about a 200 nm or so thick layer of copper, that is formed above the substrate in order to insure that the trenches/vias 14 in the layer of insulating material are completely filled. This excess copper material must be removed and it is typically removed by performing a CMP process that is expensive and time-consuming to perform. After the copper CMP process is performed, a separate CMP process is typically performed to remove excess amounts of the barrier layer 16 that is positioned outside of the trench/via 14. Achieving planar surfaces on underlying layers of material is very important so as not to adversely impact subsequent processing operations. Performing the copper CMP process to remove such a relatively large amount of bulk copper material can lead to undesirable topography differences across the substrate. Additionally, in an electroplating process, the amount of copper deposited may not be uniform across the substrate because the underneath seed layer is thin and has relatively high resistance. Lastly, to be effective, the electroplating process requires that the copper seed layer 18 uniformly cover the entirety of the wafer. However, as device dimensions have decreased and packing densities have increased, it is becoming more difficult to make the copper seed layer 18 with a uniform thickness in all areas across the substrate due to confined feature spaces.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.